A. Field of the Invention
The present invention relates to a high withstand voltage semiconductor device using a wide band gap semiconductor such as silicon carbide semiconductor (hereinafter abbreviated to as SiC) or gallium nitride semiconductor (hereinafter abbreviated to as GaN) with a wider band gap than the band gap of silicon semiconductor (hereinafter abbreviated to Si), and a method for producing the same.
B. Description of the Related Art
In many cases, Si has been heretofore used as a semiconductor substrate material of a power semiconductor device for controlling a large current while withstanding a high voltage. There are several kinds of Si power semiconductor devices. At present, the several kinds of Si power semiconductor devices are used for various purposes. Bipolar transistors or IGBTs (insulated gate bipolar transistors) are capable of gaining high current density, but unsuited to high-speed switching. For example, the frequency used in bipolar transistors is limited to the order of kHz and the frequency used in IGBTs is limited to the order of tens of kHz. On the other hand, power MOSFETs cannot be subjected to a large current but can be used for high-speed switching up to the order of MHz. There is, however, an increasing market demand for power semiconductor devices satisfying both large current characteristic and high-speed switching characteristic. Efforts have been made to improve IGBTs and power MOSFETs, so that the improvement substantially approaches the physical limit of Si material at present.
On the other hand, there is a discussion about semiconductor substrate materials other than Si because the improvement of Si power semiconductor devices approaches a physical limit of Si as described above. For example, SiC has attracted attention as a substrate material for next-generation power semiconductor devices because SiC has excellent physical properties such as low on-voltage and high-speed and high-temperature characteristic (Shenai, IEEE Transaction on Electron Devices, Vol. 36, p. 1811, 1989). SiC is a chemically highly stable material having characteristics such that SiC can be used extremely stably as a semiconductor even at a high temperature because the band gap of SiC is as wide as 3 eV. Moreover, SiC has such characteristics that the maximum electric field intensity of SiC to cause an avalanche breakdown in a semiconductor substrate is larger by at least one digit than that of Si. This characteristic can apply to GaN which is another wide band gap semiconductor material.
As described above, power MOSFETs excellent in high-speed characteristic among representative power semiconductor devices are roughly classified into two groups in terms of structure. That is, there are a planar gate structure MOSFET and a trench gate structure MOSFET.
FIG. 40 is a sectional view showing important part of a general trench gate type MOSFET. N base layer 102 and p base layer 103 are provided on high impurity concentration n+ Si substrate 101 (referred to as “n+ sub.” in FIG. 40). Each n+ source region 105 is selectively formed on a front surface of p base layer 103. Trenches 108 are provided to have a depth extending from surfaces of n+ source regions 105 to reach n base layer 102. Each trench 108 is filled with gate electrode 107 through gate insulating film 106-1. Source electrode 109 is provided as a common layer in contact with the surfaces of n+ source regions 105 and with surfaces of p+ contact regions 104 adjacent to n+ source regions 105. Drain electrode 110 having a Ni/Ti/Au laminated film is further provided on the other surface of high impurity concentration n+ Si substrate 101.
FIGS. 37 to 40 are sectional views of important part showing well-ordered illustration of a process for production of the trench gate type MOSFET. As shown in FIG. 37, n base layer 102 and p base layer 103 are formed successively on high impurity concentration n+ Si substrate 101 (referred to as “n+ sub.” in FIGS. 37, 38 and 39) by epitaxial growth or impurity diffusion. As shown in FIG. 38, n+ source region 105 and p+ contact region 104 are further formed on a front surface of p base layer 103 by selective ion implantation or the like. As shown in FIG. 39, trenches 108 each having a depth extending from a surface portion of n+ source region 105 to reach n base layer 102 through n+ source region 105 and p base layer 103 are then formed by etching.
Then, gate insulating film 106-1 and a gate electrode film are formed successively on the whole surface of each trench 108. As shown in FIG. 40, the formed gate electrode film is etched and each trench 108 is filled with a gate electrode 107 through the gate insulating film 106-1. Each gate electrode 107 is covered with interlayer insulating film 106-2 so that gate electrodes 107 can be electrically insulated from a source electrode which will be put over gate electrodes 107. Then, a Ni/Ti film provided as a common layer in contact with a surface of n+ source region 105 selectively formed on the front surface of p base layer 103 and with a surface of p+ contact layer 104 formed so as to be adjacent to n+ source region 105 and source electrode 109 made of an Al film laminated on the Ni/Ti film are formed successively by sputtering or the like. Drain electrode 110 having a Ni/Ti/Au film is further formed successively on the other surface of high impurity concentration n+ Si substrate 101 by sputtering etc. In this manner, a process of producing a wafer for the trench gate type MOSFET is completed.
If a wide band gap semiconductor is used in place of Si for forming the trench gate type MOSFET shown in FIG. 40, a high electric field causes a dielectric breakdown of SiO2 film 106-1 on the bottom of each trench 108 before the semiconductor substrate reaches an avalanche breakdown electric field when a high voltage is applied between source 109 and drain 110 of the MOSFET because the maximum electric field intensity of the wide band gap semiconductor material is higher than that of Si. For example, in the case of an SiC trench gate type MOSFET, a production method in which a p-type region (not shown) is provided on the bottom of each trench in the trench gate structure to prevent the gate oxide film from being subjected to an electric field larger than the allowable electric field is known as a method to avoid the dielectric breakdown (IEEE Transaction on Electron Devices, Vol. 38, p. 303, 1991).
FIG. 41 is a circuit diagram showing a three-phase inverter IGBT module which is a typical power semiconductor module. In the IGBT module made of this circuit, Si IGBT chips, Si free-wheeling diodes (FWDs), etc. are placed between main current-applied terminals P, N, U, V and W on a common metal substrate so as to be arranged and wired as illustrated in the circuit of FIG. 41. In such an IGBT module, an upper arm device gate drive circuit and a lower arm device gate drive circuit are connected to each IGBT. These drive circuits are connected to a control circuit while electrically insulated by photo couplers respectively. Generally, each gate drive circuit includes a forward bias source and a backward bias source. That is, one lower arm power source and three upper arm power sources, i.e., four power sources in total, are required for driving the IGBT module forming the three-phase inverter circuit shown in FIG. 41. Consequently, the circuit configuration is complicated and the apparatus size is enlarged, so that the cost increases. This is caused by the fact that n-channel IGBTs all equal in polarity are used as IGBTs mounted in the IGBT module. A complementary IGBT module having n-channel IGBTs and p-channel IGBTs reverse in polarity to the n-channel IGBTs is known as the structure of an IGBT module to reduce the cost of the expensive IGBT module structure (JP-A-63-253720 and 2001-85612).
FIG. 42 is a circuit diagram showing a three-phase inverter IGBT module using the complementary IGBT module. In FIG. 42, p-channel IGBTs are disposed in lower arms and n-channel IGBTs are disposed in upper arms while FWDs are disposed in reverse parallel with the IGBTs respectively in the same manner as in FIG. 41. In the circuit configuration of the complementary IGBT module, the number of gate drive power sources can be reduced from four to three, so that reduction in apparatus size and reduction in cost can be expected. Although it is necessary to set a dead time of the order of μsec at turning-on/off timing in the circuit shown in FIG. 41 to avoid short-circuiting caused by simultaneous on-states of the upper and lower arms, the dead time can be reduced in the case of the complementary IGBT module. Consequently, there is a merit that distortion in output waveform can be reduced. However, the complementary IGBT module has not been put into practice currently. The reason is that the complementary IGBT module is so low in avalanche breakdown tolerance that there arises a problem that the bipolar operation of the p-channel IGBTs leads to device breakdown theoretically soon (IEEE Transaction on Electron Devices, Vol. 38, p. 303, 1991).
Therefore, if unipolar power MOSFETs are used as switching devices in place of the IGBTs, the problem that device breakdown occurs theoretically easily can be solved. However, such a complementary MOSFET module has not been available on the market yet because MOSFETs have a disadvantage of being apt to be very high in on-resistance compared with the IGBTs so that the loss produced in the MOSFETs is large.
If SiC trench gate type MOSFETs (hereinafter abbreviated as trench MOSFETs) are used to form the aforementioned inverter circuit, it is further necessary to connect diodes (FWDs) in reverse parallel with the SiC trench MOSFETs. Therefore, for example, in the case of a general Si MOSFET, for reduction in size a built-in PIN diode including p base layer 103, n base layer 102 and n+ substrate 101 as shown in FIG. 40 may be used as an FWD. In this case, there is, however, a problem that switching loss still increases because the reverse recovery time of the built-in PIN diode is delayed by implantation of minority carriers even when the built-in PIN diode is electrically connected as the FWD. It has been known that the problem of increase in loss at the reverse recovery time can be avoided when a Schottky barrier diode of a unipolar operation is formed as the built-in diode in place of the PIN diode. See, for example, FIG. 1 of JP-A-2005-57291 (Corresponding to US 2005029585), JP-A-8-204179 (Corresponding to U.S. Pat. No. 5,614,749), U.S. Pat. No. 5,693,569, U.S. Pat. No. 5,614,749, and JP-A-9-102602.
It is, however, very difficult to produce a low-resistance low-defect-density p-type semiconductor substrate from a wide band gap semiconductor, especially from SiC or GaN. For example, in the existing situation, the resistivity of the p-type semiconductor substrate produced from SiC is more than ten times as high as that of the n-type semiconductor substrate and the defect density of the p-type semiconductor substrate produced from SiC is higher by at least one digit than that of the n-type semiconductor substrate. For this reason, there arises a problem that on-resistance cannot be reduced sufficiently because the potential drop in the p-type semiconductor substrate is large even when the p-type semiconductor substrate is used for forming a p-channel MOSFET.
Because it is highly likely that SiC or GaN will overcome the physical limit of Si, the extension of SiC or GaN for power semiconductor purposes, especially, MOSFET purposes, is expected to increase greatly in the future. If a p-channel MOSFET can be produced from SiC or GaN, a high withstand voltage complementary module which could not be achieved when Si IGBTs were used can be expected because a complementary MOSFET module can be formed when p-channel MOSFETs are used in combination with n-channel MOSFETs produced from SiC or GaN.
On the other hand, the SiC trench MOSFET has a problem that a very difficult and time-consuming process is required for accurately forming an electric field relaxing p-type region described in IEEE Transaction on Electron Devices, 38:303, (1991), in the bottom of the trench of the trench gate having a fine pattern structure (Addamiano et al., Journal of the Electrochemical Society, 11 (9):1355 (1972) or Gusev et al., Sov. Phys. Semicond., 9:820 (1976)).
Further, when the electric field relaxing p-type region is formed, a storage layer for turning the MOSFET on is lost. Consequently, there is a problem that increase of on-resistance cannot be avoided. Accordingly, there is a demand for an MOSFET having a structure in which dielectric breakdown of the gate oxide film can be prevented from being caused by the high electric field intensity and long-term reliability can be kept without provision of the p-type region in the bottom of the trench of the trench gate.
There is another problem that loss increases at the time of current conduction and reverse recovery of current conduction of the PIN diode built in the trench MOSFET made of a wide band gap semiconductor as described above even when the breakdown of the gate insulating film can be prevented from being caused by the high electric field intensity. It is therefore necessary to improve this aspect.
That is, in the SiC trench MOSFET, the diffusion potential difference between p base layer 103 and n base layer 102 in FIG. 40 is large. For example, when the MOSFET is made of SiC, the diffusion potential difference is about 2.7 V. For this reason, the on-voltage of the built-in PIN diode (p base layer 103/n base layer 102/n+ substrate 101) in the SiC MOSFET is very high compared with the typical on-voltage 1.6-2.0 V of the built-in PIN diode of the Si MOSFET. The loss incurred in the SiC MOSFET in an on-state is large. There arises a further problem that switching loss increases because the reverse recovery time of the built-in PIN diode is delayed by implantation of minority carriers even when a current flows in the built-in PIN diode. It already has been known that the problem about increase of loss at the time of reverse recovery can be avoided when a Schottky barrier diode having a unipolar operation is formed as the built-in diode as described above. That is, the Schottky barrier diode can reduce power loss because on-resistance in the wide band gap semiconductor such as SiC or GaN can be reduced and a low reverse recovery loss and a sufficient peak inverse voltage can be kept due to the unipolar device. There is further known a structure in which the formation of the Schottky barrier diode is optimized to give an effect to the aforementioned trench gate structure in reducing the electric field intensity applied on the oxide film in the bottom of the trench. It is, however, impossible to form a selective p-type region or the like by ion implantation as controllably as in Si in the case of the wide band gap semiconductor MOSFET such as SiC or GaN. For this reason, it is very difficult to arrange an n base layer which is selectively arranged on the device surface in the active region and which needs to form Schottky barrier contact in its surface. Consequently, it cannot be said practically that it is easy to build a Schottky barrier diode in the active region of the wide band gap semiconductor MOSFET, differently from Si.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.